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PRELIMINARY
FEMTOCLOCKSTM CRYSTAL-TO-3.3V, 2.5V LVPECL 75MHZ FREQUENCY SYNTHESIZER W/SSC
ICS843301I-108
GENERAL DESCRIPTION
The ICS843301I-108 is a 75MHz Frequency IC S Generator and a member of the HiPerClocks TM HiPerClockSTM family of high perfor mance devices from IDT. The ICS843301I-108 uses a 20MHz crystal to synthesize 75MHz output. The device supports 0.5% downspread spread spectrum clocking. The ICS843301I108 has excellent <1ps phase jitter performance, over an integration range of 900kHz - 7.5MHz. The device is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
FEATURES
* One differential 3.3V or 2.5V LVPECL output * Crystal oscillator interface designed for 20MHz, 18pF parallel resonant crystal * Output frequency: 75MHz * Supports SSC, 0.5% downspread * RMS phase jitter @ 75MHz, using a 20MHz crystal (900kHz - 7.5MHz): 0.73ps (typical) * Full 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
SSC FUNCTION TABLE
Input SSC 0 (default) 1 Mode SSC Off 0.5% Downspread
BLOCK DIAGRAM
20MHz XTAL_IN
PIN ASSIGNMENT
VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ SSC
PLL Phase Detector VCO
600MHz
OSC
XTAL_OUT
N Div /8
Q nQ
ICS843301I-108
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
SSC
Pulldown
M Div /30
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6, 7 8 Name VCCA VEE XTAL_OUT, XTAL_IN SSC nQ, Q VCC Power Power Input Input Output Power Type Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown SSC control pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Core and output supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Pin Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 101.7C/W (0 mps)
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA ICCA IEE Parameter Core Supply Voltage Analog Supply Voltage Analog Supply Current Power Supply Current Test Conditions Minimum 3.135 VCC - 0.10 Typical 3. 3 3. 3 10 106 Maximum 3.465 VCC Units V V mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA ICCA IEE Parameter Core Supply Voltage Analog Supply Voltage Analog Supply Current Power Supply Current Test Conditions Minimum 2.375 VCC - 0.09 Typical 2.5 2. 5 9 100 Maximum 2.625 VCC Units V V mA mA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V -5 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0. 8 0.7 15 0 Units V V V V A A
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum Typical Fundamental 20 90 7 300 MHz pF W Maximum Units
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fOUT tjit(O) FM FMF SSCred t R / tF Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 SSC Modulation Frequency; NOTE 3 SSC Modulation Factor; NOTE 3 Spectral Reduction; NOTE 3 Output Rise/Fall Time Test Conditions 75MHz (Integration Range: 900kHz - 7.5MHz) FOUT = 75MHz FOUT = 75MHz FOUT = 75MHz 20% to 80% 29 0.5 8 475 50 Minimum Typical 75 0.73 33.33 Maximum Units MHz ps kHz % dB ps %
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Spread Spectrum clocking disabled. NOTE 3: Spread Spectrum clocking enabled.
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol Parameter fOUT tjit(O) FM FMF SSCred t R / tF Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 SSC Modulation Frequency; NOTE 3 SSC Modulation Factor; NOTE 3 Spectral Reduction; NOTE 3 Output Rise/Fall Time Test Conditions 75MHz (Integration Range: 900kHz - 7.5MHz) FOUT = 75MHz FOUT = 75MHz FOUT = 75MHz 20% to 80% 29 0.4 7.5 450 50 Minimum Typical 75 0.72 33.33 Maximum Units MHz ps kHz % dB ps %
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Spread Spectrum clocking disabled. NOTE 3: Spread Spectrum clocking enabled.
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V 2V 2V 2V
VCC VCCA
Qx
SCOPE
VCC VCCA
Qx
SCOPE
LVPECL
nQx VEE
LVPECL
nQx VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
VOH VREF VOL
80% Clock Outputs
80% VSW I N G
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
20% tR tF
20%
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT RISE/FALL TIME
nQ Q
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843301I-108 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VCCA pin.
3.3V or 2.5V VCC .01F 10
VCCA .01F 10F
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843301I-108 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 20MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 X1 Crystal XTAL_OUT C2
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER
TO
XTAL INPUT INTERFACE
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32kHz triangle waveform is used with 0.5% down-spread (+0.0% / TBD%) from the nominal 75MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 4A below. The ICS843301I-108 triangle modulation frequency deviation will not exceed TBD% down-spread from the nominal clock frequency (+0.0% / TBD%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 4B. The ratio of this difference to the fundamental frequency is typically 0.5%, and will not exceed TBD%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 4B. It is important to note the ICS843301I-108 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. - 8 dBm
Fnom
B
A
(1 - ) Fnom
= 0.5%
0.5/fm 1/fm
FIGURE 4A. TRIANGLE FREQUENCY MODULATION
FIGURE 4B. 75MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C.
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843301I-108. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843301I-108 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 106mA = 367.29mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 370.75mW + 30mW = 397.29mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.397W * 90.5C/W = 120.9C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL 50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V
*
For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) =
L L
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) =
L L
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS843301I-108 is: 3792
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
PACKAGE OUTLINE - G SUFFIX 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number 843301BGI-108 843301BGI-108T 843301BGI-108LF 843301BGI-108LFT Marking BI108 BI108 B108L BI08L Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER W/SSC
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PRELIMINARY
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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